DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 592

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.23 Notes on Output Waveform Control During Synchronous Counter Clearing in
In complementary PWM mode, when output waveform control during synchronous counter
clearing is enabled (WRE in the TWCR register set to 1), the following problems may occur when
condition (1) or condition (2), below, is satisfied.
• Dead time for the PWM output pins may be too short (or nonexistent).
• Active-level output from the PWM negative-phase pins may occur outside the correct active-
Condition (1): When synchronous clearing occurs in the PWM output dead time interval within
Condition (2): When synchronous clearing occurs within initial output suppression interval (10) or
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level output interval
PWM output
(positive phase)
PWM output
(negative phase)
Complementary PWM Mode
TGRA_3
TDDR
TGR
initial output suppression interval (10) (figure 12.125).
(11) and TGRB_3 ≤ TDDR, TGRA_4 ≤ TDDR, or TGRB_4 ≤ TDDR is true
(figure 12.126)
0
Figure 12.125 Condition (1) Synchronous Clearing Example
TCNT4
TCNT3
TDDR
(10)
Tb interval
(11)
Shortened dead time
Synchronous clearing
Note: PWM output is low-active.
Initial output suppression
Dead time
(10)
Tb interval
(11)
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010