DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 915

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
Typical operations when a single channel (AN1) is selected in single mode are described next.
Figure 20.2 shows a timing diagram for this example (the bits which are set in this example belong
to ADCSR).
1. Single mode is selected, input channel AN1 is selected (CH2 = 0, CH1 = 0, CH0 = 1), the A/D
2. When A/D conversion is completed, the A/D conversion result is transferred into ADDRB. At
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The routine reads ADF = 1, and then writes 0 to the ADF flag.
6. The routine reads and processes the A/D conversion result (ADDRB).
7. Execution of the A/D interrupts handling routine ends. Then, when the ADST bit is set to 1,
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter
becomes idle.
A/D conversion starts and steps 2. to 7. are executed.
Section 20 A/D Converter (ADC)
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