DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 869

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
Bit 8 - Mailbox Empty Interrupt Flag (IRR8): This bit is set when one of the messages set for
transmission has been successfully sent (corresponding TXACK flag is set) or has been
successfully aborted (corresponding ABACK flag is set). The related TXPR is also cleared and
this mailbox is now ready to accept a new message data for the next transmission. In effect, this
bit is set by an OR'ed signal of the TXACK and ABACK bits not masked by the corresponding
MBIMR flag. Therefore, this bit is automatically cleared when all the TXACK and ABACK bits
are cleared. It is also cleared by writing a '1' to all the correspondent bit position in MBIMR.
Writing to this bit position has no effect.
Bit 7 - Overload Frame (IRR7): Flag indicating that the RCAN-ET has detected a condition that
should initiate the transmission of an overload frame. Note that on the condition of transmission
being prevented, such as listen only mode, an Overload Frame will NOT be transmitted, but IRR7
will still be set. IRR7 remains asserted until reset by writing a '1' to this bit position - writing a '0'
has no effect.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit 8: IRR8
0
1
Bit 7: IRR7
0
1
Description
Messages set for transmission or transmission cancellation request NOT
progressed. (Initial value)
[Clearing Condition] All the TXACK and ABACK bits are cleared/setting
MBIMR for all TXACK and ABACK set
Message has been transmitted or aborted, and new message can be stored
[Setting condition]
When one of the TXPR bits is cleared by completion of transmission or
completion of transmission abort, i.e., when a TXACK or ABACK bit is set
(if MBIMR = 0).
Description
[Clearing condition] Writing 1 (Initial value)
[Setting conditions] Overload condition detected
Section 19 Controller Area Network (RCAN-ET)
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