DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 198

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 7 User Break Controller (UBC)
7.3.6
BRCR sets the following conditions:
1. Specifies whether a start of user break interrupt exception processing by instruction fetch cycle
2. Specifies the pulse width of the UBCTRG output when a break condition is satisfied.
BRCR is a 32-bit readable/writable register that has break condition match flags and bits for
setting other break conditions. For the condition match flags of bits 15 to 12, writing 1 is invalid
(previous values are retained) and writing 0 is only possible. To clear the flag, write 0 to the flag
bit to be cleared and 1 to all other flag bits. BRCR is initialized to H'00000000 by a power-on
reset and in deep standby, but retains its previous value by a manual reset or in software standby
mode or sleep mode.
Page 170 of 1190
Bit
31 to 18
17, 16
Initial value:
Initial value:
is set before or after instruction execution.
R/W:
R/W:
Bit:
Bit:
Break Control Register (BRCR)
SCMFC
R/W
Bit Name
⎯
CKS[1:0]
31
15
R
0
0
0
SCMFC
R/W
30
14
R
0
1
0
SCMFD
R/W
29
13
R
0
0
0
Initial
Value
All 0
00
SCMFD
R/W
28
12
R
0
0
1
27
11
R
R
0
0
R/W
R
R/W
26
10
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Select
Specifies the pulse width output to the UBCTRG pin
when a break condition is satisfied.
00: Pulse width of UBCTRG is one bus clock cycle
01: Pulse width of UBCTRG is two bus clock cycles
10: Pulse width of UBCTRG is four bus clock cycles
11: Pulse width of UBCTRG is eight bus clock cycles
25
R
R
0
9
0
24
R
R
0
8
0
23
R
R
0
7
0
PCB1 PCB0
R/W
22
R
0
6
0
R/W
21
R
0
5
0
20
R
R
0
4
0
R01UH0026EJ0300 Rev. 3.00
19
R
R
0
3
0
18
R
R
2
0
0
SH7201 Group
R/W
17
Sep 24, 2010
R
CKS[1:0]
0
1
0
R/W
16
R
0
0
0