DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 246

IC SH7201 MPU ROMLESS 176LQFP

DS72011RB120FPV

Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet

Specifications of DS72011RB120FPV

Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus State Controller (BSC)
Page 218 of 1190
Bit
22 to 20 WRON
19
18 to 16 RDON
15 to 11 ⎯
10 to 8
7
Bit Name
[2:0]
[2:0]
WDOFF
[2:0]
Initial
Value
000
0
000
All 0
000
0
R/W
R/W
R
R/W
R
R/W
R
Description
WR Assert Wait Select
These bits specify the number of wait states inserted
before the external data write signal (WR3 to WR0) is
asserted.
000: 0 wait state
111: 7 wait states
Reserved
This bit is always read as 0. The write value should
always be 0.
RD Assert Wait Select
These bits specify the number of wait states inserted
before the external data read signal (RD) is asserted.
000: 0 wait state
111: 7 wait states
Reserved
These bits are always read as 0. The write value
should always be 0.
Write Data Output Delay Cycle Select
These bits specify the number of cycles from the end of
the wait cycle during write operation (negation of the
WR3 to WR0 signals) and the negation of the external
data bus.
000: 0 wait state
111: 7 wait states
Reserved
This bit is always read as 0. The write value should
always be 0.
:
:
:
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010

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