DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 478

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.42 Setting of Bits BTE1 and BTE0
Notes: 1. Data is transferred according to the MD3 to MD0 bit setting in TMDR. For details, refer
Page 450 of 1190
Bit 1
BTE1
0
0
1
1
2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the
to section 12.4.8, Complementary PWM Mode.
timer interrupt skipping set register (TITCR) or the skipping count set bits (3ACOR and
4VCOR) in TITCR are cleared to 0)), be sure to disable link of buffer transfer with
interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to
0). If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer
transfer will not be performed.
Bit 0
BTE0
0
1
0
1
Description
Enables transfer from the buffer registers to the temporary registers*
and does not link the transfer with interrupt skipping operation.
Disables transfer from the buffer registers to the temporary registers.
Links transfer from the buffer registers to the temporary registers with
interrupt skipping operation.*
Setting prohibited
2
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010
1