DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 257

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
9.4.14
SDmTR specifies the timing for read and write accesses to SDRAM.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
31 to 19 ⎯
18 to 16 DRAS[2:0] Undefined R/W
15, 14
13, 12
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
SDRAMm Timing Register (SDmTR) (m = 0, 1)
Bit Name
⎯
DRCD[1:0] Undefined R/W
31
15
—
—
R
R
0
0
30
14
—
—
R
R
0
0
R/W
DRCD[1:0]
29
13
—
—
Initial
Value
All 0
All 0
R
0
R/W
28
12
—
—
R
0
R/W
27
11
—
—
R
0
R/W
R
R
DPCG[2:0]
R/W
26
10
—
—
R
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Row Active Interval Setting
These bits specify the minimum interval that must
elapse between the SDRAM row activation command
(ACT) and deactivation (PRA).
000: 1 cycle
111: 8 cycles
Reserved
These bits are always read as 0. The write value
should always be 0.
Row Column Latency Setting
These bits specify the SDRAM row column latency.
00: 1 cycles
01: 2 cycles
10: 3 cycles
11: 4 cycles
R/W
25
—
—
R
0
9
:
DWR
R/W
24
—
—
R
0
8
23
—
—
R
R
0
7
0
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
Section 9 Bus State Controller (BSC)
20
—
—
R
R
0
4
0
19
—
—
R
R
0
3
0
R/W
R/W
18
—
—
2
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DRAS[2:0]
DCL[2:0]
R/W
R/W
17
—
—
1
R/W
R/W
16
—
—
0