DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 115

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
4.5
The frequency of the internal clock (Iφ) and peripheral clock (Pφ) can be changed either by
changing the multiplication rate of PLL circuit 1 or by changing the division rates of divider. All
of these are controlled by software through the frequency control register (FRQCR). The methods
are described below.
4.5.1
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The on-
chip WDT counts the settling time.
1. In the initial state, the multiplication rate of PLL circuit 1 is 1 time.
2. Set a value that will become the specified oscillation settling time in the WDT and stop the
3. Set the desired value in the STC[2:0] bits. The division ratio can also be set in the IFC[2:0] and
4. This LSI pauses temporarily and the WDT starts incrementing. The internal and peripheral
5. Supply of the clock that has been set begins at WDT count overflow, and this LSI begins
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
WDT. The following must be set:
WTCSR.TME = 0: WDT stops
WTCSR.CKS[2:0]: Division ratio of WDT count clock
WTCNT counter: Initial counter value
PFC[2:0] bits.
clocks both stop and the WDT is supplied with the clock. The clock will continue to be output
at the CKIO pin. This state is the same as software standby mode. Whether or not registers are
initialized depends on the module. For details, see section 25, Power-Down Modes.
operating again. The WDT stops after it overflows.
Changing the Frequency
Changing the Multiplication Rate
Section 4 Clock Pulse Generator (CPG)
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