DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 313

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
The bus monitor is a module that monitors bus errors on each bus. When an illegal address access
or a bus timeout is detected, a bus error interrupt is generated and an access canceling signal is
output for the bus timeout. (The bus timeout function is used for debugging.)
Figure 10.1 shows a block diagram of the bus monitor.
10.1
The bus monitor has the following registers.
All registers are initialized by a power-on reset or in deep standby mode.
Table 10.1 Register Configuration
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Register Name
Bus monitor enable register
Bus monitor status register 1
Bus monitor status register 2
Bus error control register
Peripheral
bus
Register Descriptions
Bus monitor
Figure 10.1 Block Diagram of Bus Monitor
Section 10 Bus Monitor
Bus monitor status register 1
Bus monitor status register 2
Abbreviation
SYCBEEN
SYCBESTS1
SYCBESTS2
SYCBESW
Bus monitor enable register
Bus error control register
R/W
R/W
R/W
R/W
R/W
Initial Value
H'00
H'00
H'00
H'00
Bus error signal
Address
H'FF400000
H'FF400004
H'FF400008
H'FF40000C 8, 16, 32
Section 10 Bus Monitor
CPU core
SH2A
Page 285 of 1190
Access
Size
8, 16, 32
8, 16, 32
8, 16, 32