DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1196

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Main Revisions for This Edition
Page 1168 of 1190
Item
12.4.8 Complementary PWM
Mode
(2) Outline of Complementary
PWM Mode Operation
(n) Output Waveform Control at
Synchronous Counter Clearing in
Complementary PWM Mode
(3) Interrupt Skipping in
Complementary PWM Mode:
(c) Buffer Transfer Control Linked
with Interrupt Skipping
Figure 12.71 Example of
Operation when Buffer Transfer is
Linked with Interrupt Skipping
(BTE1 = 1 and BTE0 = 0)
Figure 12.72 Relationship
between Bits T3AEN and T4VEN
in TITCR and Buffer Transfer-
Enabled Period
12.5.3 A/D Converter Activation
(3) A/D Converter Activation by
A/D Converter Start Request
Delaying Function
12.7.23 Notes on Output
Waveform Control During
Synchronous Counter Clearing in
Complementary PWM Mode
14.5.3 Interval Timer Overflow
Flag
Page
509
522
523
535
564,
565
636
Revision (See Manual for Details)
Description added
... suppressed.
When using the initial output suppression function,
make sure to set compare registers TGRB_3,
TGRA_4, and TGRB_4 to a value twice or more the
setting of dead time data register TDDR. If
synchronous clearing occurs with the compare
registers set to a value less than twice the setting of
TDDR, the PWM output dead time may be too short
(or nonexistent) or illegal active-level PWM negative-
phase output may occur during the initial output
suppression interval. For details, see section 12.7.23,
Notes on Output Waveform Control During
Synchronous Counter Clearing in Complementary
PWM Mode.
Figure replaced
Figure replaced
Description amended
The A/D converter can be activated by generating A/D
converter start request signal TRG4AN or TRG4BN
when the TCNT_4 count matches the TADCORA or
TADCORB value if the UT4AE, DT4AE, UT4BE, or
DT4BE bit in the A/D converter start request control
register (TADCR) is set to 1.
Newly added
Newly added
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010