DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1194

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Main Revisions for This Edition
Page 1166 of 1190
Item
8.4.4 Notes
9.4.8 SDRAM Refresh Control
Register 1 (SDRFCNT1)
11.4.1 DMA Transfer Mode
Figure 11.2 Examples of the
Alternation of Bus Mastership
between the DMAC and CPU in
Various DMA Transfer Modes
11.4.2 DMA Transfer Condition
(1) Unit Operand Transfer
Page
198
223
341
342
Revision (See Manual for Details)
Description amended
1. Programs that access memory-mapped cache of
Description amended
DRFC = (Auto-refresh request interval / Bus clock
cycle) – 1
Figure amended
Pipeline transfer mode (transfer between different BIU)
Description added
... transfer is completed by repeating unit transfer
operations until the byte counter does reach 0.
In the case that the DMA transfer condition is the unit
operand transfer and the input sense mode of DMA
request is the level sense, there is the mask period of
the DMA request in the channel arbitration period
after one operand transfer end (please refer to section
11.7.3, Sense Mode for DMA Requests for details).
Therefore, in the channel arbitration period after one
operand transfer end, in the case that there is no
DMA request of the higher-priority channel than the
transferring channel and there is the DMA request of
the lower-priority channel than the transferring
channel, the DMA transfer of the low-priority channel
starts. To execute the DMA transfer of the high-
priority channel in succession, please set the DMA
transfer condition to the sequential operand transfer
or the non-stop transfer.
System clock
DMAC
CPU
the operand cache should be placed in a cache-
disabled space. Programs that access memory-
mapped cache of the instruction cache should be
placed in a cache-disabled space, and in each of
the beginning and the end of that, two or more
read accesses to on-chip peripheral modules or
external address space (cache-disabled address)
should be executed.
(4) CPU access to other than BIU on DMAC read side is possible
(5) CPU access to other than BIU on DMAC read/write side is possible
(6) CPU access to other than BIU on DMAC write side is possible
However, when a DMA access to external address space followed by CPU access to external address
space is occurred, CPU access next to DMA cycle may not be occurred.
Read
(4)
Single operand transfer
Read
Read
Write
(5)
Read
Write
Write
(6)
Write
Read
R01UH0026EJ0300 Rev. 3.00
(4)
Single operand transfer
Read
Read
Write
(5)
Read
Write
Write
(6)
Write
SH7201 Group
Sep 24, 2010