DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 224

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 8 Cache
(1)
The data specified by the L bit in the address is read from the entry address specified by the
address and the entry corresponding to the way.
(2)
The longword data specified by the data is written to the position specified by the L bit in the
address from the entry address specified by the address and the entry corresponding to the way.
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(b) Data specification (both read and write accesses)
1.2 Data array access (both read and write accesses)
(a) Address specification
(b) Data specification
1. Instruction cache
1.1 Address array access
(a) Address specification
111100000
111100000
[Legend]
*:
E:
X:
Read access
Write access
111100010
31
31
31
31
31
0 0 0
Don't care
Bit 10 of entry address for read, don't care for write
0 for read, don't care for write
Data Array Read
Data Array Write
29 28
Tag address (28 to 11)
23 22
23 22
23 22
Figure 8.4 Specifying Address and Data for Memory-Mapped Cache Access
*----------*
*----------*
*----------*
13 12 11
13 12 11 10
13 12 11 10
Longword data
W
W
W
11 10 9
10
E
Entry address
Entry address
Entry address
LRU
4
4
4
4
0
A
X
3
3
3
3
L
2
*
2
*
2
X
2
X
1
0
1
0
1
1
0
V
0
0
0
0
0
0
0
0
(b) Data specification (both read and write accesses)
2.2 Data array access (both read and write accesses)
(a) Address specification
(b) Data specification
2. Operand cache
2.1 Address array access
(a) Address specification
111100001
111100001
Read access
Write access
111100011
31
31
31
31
31
0 0 0
29 28
Tag address (28 to 11)
23 22
23 22
23 22
*----------*
*----------*
*----------*
13 12 11
13 12 11 10
13 12 11 10
W
W
W
11 10 9
Longword data
10
E
R01UH0026EJ0300 Rev. 3.00
Entry address
Entry address
Entry address
LRU
4
4
4
4
SH7201 Group
3
0
3
A
3
X
3
Sep 24, 2010
L
2
*
2
*
2
X
2
U
1
0
1
0
1
1
0
V
0
0
0
0
0
0
0
0