DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1056
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 27 Advanced User Debugger II (AUD-II)
(1) Description of Pins
Table 27.2 Description of Pins
Page 1028 of 1190
Pin
AUDMD
AUDRST
AUDCK
AUDSYNC
AUDATA[3:0]
Function
The mode is selected by changing the input level at this pin.
Low: Setting prohibited
High: RAM monitor mode
The input at this pin should be changed when AUDRST is low.
When this pin is driven low, the AUD enters the reset state and the AUD's
internal buffers and logic are reset. When AUDRST goes high again after the
AUDMD level settles, the AUD starts operating in the selected mode.
Note that the available frequency is up to Bφ/2.
AUD Bus Command Valid Signal
1: Read data is output
0: Inputs write address, data, DIR command
•
•
•
When a command is input from outside, data is output after Ready is
transmitted. The output starts after AUDSYNC is negated. For details, see the
protocol as described later.
This pin is for external clock input. Input the clock to be used for debugging.
The following data is output in time-sharing mode.
Note: Do not assert this pin until commands are input to AUDATA from
AUD bus command
Address
Data
outside and necessary data is prepared. For details, see the protocol
as described later.
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010
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