DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 128

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 5 Exception Handling
5.2.4
(1)
When the MRES pin is driven low, this LSI enters the manual reset state. To reset this LSI without
fail, the MRES pin should be kept at the low level for at least 20-tcyc. In the manual reset state,
the CPU’s internal state is initialized, but all the on-chip peripheral module registers are not
initialized. In the manual reset state, manual reset exception handling starts when the MRES pin is
first driven low for a fixed period and then returned to high. The CPU operates as follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to
4. The values fetched from the exception handling vector table are set in the PC and SP, and the
(2)
When a setting is made for a manual reset to be generated in the WDT’s watchdog timer mode,
and WTCNT of the WDT overflows, this LSI enters the manual reset state.
When manual reset exception processing is started by the WDT, the CPU operates in the same
way as when a manual reset was caused by the MRES pin.
(3)
When a manual reset is generated, the bus cycle is retained. Thus, manual reset exception handling
will be deferred until the CPU acquires the bus mastership. The CPU and the BN bit in IBNR of
the INTC are initialized by a manual reset. The FPU and other modules are not initialized.
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exception handling vector table.
I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are
initialized. The BN bit in IBNR of the INTC is also initialized to 0.
program begins executing.
Manual Reset by Means of MRES Pin
Manual Reset Initiated by WDT
Notes at a Manual Reset
Manual Reset
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010