DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 502

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(1)
(2)
Figure 12.26 shows an example of PWM mode 1 operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers
are used as the duty levels.
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Figure 12.25 shows an example of the PWM mode setting procedure.
Example of PWM Mode Setting Procedure:
Examples of PWM Mode Operation
TGRA
TGRB
H'0000
TIOCA
Select counter clearing source
Select waveform output level
Select counter clock
TCNT value
Figure 12.25 Example of PWM Mode Setting Procedure
Set PWM mode
<PWM mode>
Figure 12.26 Example of PWM Mode Operation (1)
PWM mode
Start count
Set TGR
[1]
[2]
[3]
[4]
[5]
[6]
Counter cleared by
TGRA compare match
[1] Select the counter clock with bits TPSC2 to
[2] Use bits CCLR2 to CCLR0 in TCR to select
[3] Use TIOR to designate the TGR as an output
[4] Set the cycle in the TGR selected in [2], and
[5] Select the PWM mode with bits MD3 to MD0
[6] Set the CST bit in TSTR to 1 to start the
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and
CKEG0 in TCR.
the TGR to be used as the TCNT clearing
source.
compare register, and select the initial value
and output value.
set the duty in the other TGR.
in TMDR.
count operation.
R01UH0026EJ0300 Rev. 3.00
Time
SH7201 Group
Sep 24, 2010