DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 149

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
6.3.2
ICR0 is a 16-bit register that sets the input signal detection mode for the external interrupt input
pin NMI, and indicates the input level at the NMI pin. ICR0 is initialized by a power-on reset or in
deep standby mode.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
15
14 to 9
8
7 to 0
Initial value:
Note: * 1 when the NMI pin is high, and 0 when the NMI pin is low.
R/W:
Bit:
Interrupt Control Register 0 (ICR0)
Bit Name
NMIL
⎯
NMIE
⎯
NMIL
15
R
*
14
—
R
0
13
—
R
0
Initial
Value
*
All 0
0
All 0
12
—
R
0
11
—
R
0
R/W
R
R
R/W
R
10
—
R
0
Description
NMI Input Level
Sets the level of the signal input at the NMI pin. The
NMI pin level can be obtained by reading this bit. This
bit cannot be modified.
0: Low level is input to NMI pin
1: High level is input to NMI pin
Reserved
These bits are always read as 0. The write value should
always be 0.
NMI Edge Select
Selects whether the falling or rising edge of the
interrupt request signal on the NMI pin is detected.
0: Interrupt request is detected on falling edge of NMI
1: Interrupt request is detected on rising edge of NMI
Reserved
These bits are always read as 0. The write value should
always be 0.
—
R
9
0
input
input
NMIE
R/W
8
0
—
R
7
0
—
R
6
0
—
R
5
0
Section 6 Interrupt Controller (INTC)
—
R
4
0
—
R
3
0
—
R
2
0
Page 121 of 1190
—
R
1
0
—
R
0
0