DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 227

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
The bus state controller (BSC) outputs control signals for various types of memory that is
connected to the external address space and external devices. This enables the LSI to connect
directly with SRAM, SDRAM, and other memory storage devices, and external devices.
9.1
1. External address space
• A maximum of 64 Mbytes for the SDRAM and each for areas CS0 to CS6 (256 Mbytes for
• Ability to select the data bus width (8, 16, or 32 bits) independently for each address space
2. Normal space interface
• Supports an interface for direct connection to SRAM
• Cycle wait function: Maximum of 31 wait states (maximum of seven wait states for page
• Wait control
• Write access modes: One-write strobe and byte-write strobe modes
• Page access mode: Support for page read and page write (64-bit, 128-bit, and 256-bit page
3. SDRAM interface
• Ability to set SDRAM in up to two areas
• Refresh functions
• Ability to select the access timing (support for low column latency, column latency, and low
• Initialization sequencer function, power-down function, deep-power-down function, and mode
Figure 9.1 shows a block diagram of the BSC.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
CS6)
access cycles)
⎯ Ability to select the assert/negate timing for chip select signals
⎯ Ability to select the assert/negate timing for the read strobe and write strobe signals
⎯ Ability to select the data output start/end timing
⎯ Ability to select the delay for chip select signals
units)
⎯ Auto-refresh (on-chip programmable refresh counter)
⎯ Self-refresh
active interval settings)
register setting function implemented on-chip
Features
Section 9 Bus State Controller (BSC)
Section 9 Bus State Controller (BSC)
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