DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 57

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
(11) Absolute Address
When data is accessed by an absolute address, the absolute address value should be placed in the
memory table in advance. That value is transferred to the register by loading the immediate data
during the execution of the instruction, and the data is accessed in register indirect addressing
mode.
With the SH-2A, when data is referenced using an absolute address not exceeding 28 bits, it is also
possible to transfer immediate data located in the instruction code to a register and to reference the
data in register indirect addressing mode. However, when referencing data using an absolute
address of 21 to 28 bits, an OR instruction must be used after the data is transferred to a register.
Table 2.6
(12) 16-Bit/32-Bit Displacement
When data is accessed by 16-bit or 32-bit displacement, the displacement value should be placed
in the memory table in advance. That value is transferred to the register by loading the immediate
data during the execution of the instruction, and the data is accessed in the indexed indirect
register addressing mode.
Table 2.7
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Classification
Up to 20 bits
21 to 28 bits
29 bits or more
Classification
16-bit displacement
Absolute Address Accessing
Displacement Accessing
SH-2A CPU
MOVI20
MOV.B
MOVI20S
OR
MOV.B
MOV.L
MOV.B
.DATA.L
SH-2A CPU
MOV.W
MOV.W
.DATA.W
#H'12345,R1
@R1,R0
#H'12345,R1
#H'67,R1
@R1,R0
@(disp,PC),R1
@R1,R0
H'12345678
..................
@(disp,PC),R0
@(R0,R1),R2
..................
H'1234
Example of Other CPU
MOV.W
Example of Other CPU
MOV.B
MOV.B
MOV.B
@(H'1234,R1),R2
@H'12345,R0
@H'1234567,R0
@H'12345678,R0
Page 29 of 1190
Section 2 CPU