DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 400

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Page 372 of 1190
External clock: TCLKA
Internal clock:
TSTR: Timer start register
TSYR: Timer synchronous register
TCR:
TMDR: Timer mode register
TIOR:
TIORH: Timer I/O control register H
TIORL: Timer I/O control register L
TIER:
TGCR: Timer gate control register
[Legend]
Channel 3: TIOC3A
Channel 4: TIOC4A
Channel 0: TIOC0A
Channel 1: TIOC1A
Channel 2: TIOC2A
Channel 5: TIC5U
Input/output pins
Input/output pins
Timer control register
Timer I/O control register
Timer interrupt enable register
Clock input
Input pins
TIOC3C
TIOC3D
TIOC4C
TIOC4D
TIOC3B
TIOC4B
P /1024
TIOC0C
TIOC0D
TIOC0B
TIOC1B
TIOC2B
TIC5W
TCLKC
TCLKD
TCLKB
P /256
TIC5V
P /16
P /64
P /1
P /4
Figure 12.1 Block Diagram of MTU2
TOER: Timer output master enable register
TOCR: Timer output control register
TSR:
TCNT: Timer counter
TCNTS: Timer subcounter
TCDR:
TCBR:
TDDR:
Timer status register
Timer cycle buffer register
Timer cycle data register
Timer dead time data register
Interrupt request signals
Interrupt request signals
Channel 5: TGIU_5
Channel 3: TGIA_3
Channel 4: TGIA_4
Channel 0: TGIA_0
Channel 1: TGIA_1
Channel 2: TGIA_2
Peripheral bus
A/D converter conversion
start signal
TGRA:
TGRB:
TGRC:
TGRD:
TGRE:
TGRF:
TGRU:
TGRV:
TGRW: Timer general register W
R01UH0026EJ0300 Rev. 3.00
TGIW_5
TGIC_3
TGID_3
TGIC_4
TGID_4
TGIC_0
TGID_0
TGIB_3
TCIV_3
TGIB_4
TCIV_4
TGIV_5
TGIB_0
TGIE_0
TGIB_1
TCIU_1
TGIB_2
TCIU_2
TGIF_0
TCIV_0
TCIV_1
TCIV_2
Timer general register F
Timer general register A
Timer general register B
Timer general register E
Timer general register V
Timer general register C
Timer general register D
Timer general register U
SH7201 Group
Sep 24, 2010