DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 354

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Direct Memory Access Controller (DMAC)
11.3.9
DMCNTB enables or disables DMA transfer, clears the DMA transfer enable bit, and also clears
the internal state. In addition, this register can check the status of a DMA request.
Page 326 of 1190
Bit
31 to 25 ⎯
24
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
DMA Control Register B (DMCNTB)
Bit Name
DEN
31
15
—
—
R
R
0
0
30
—
14
—
R
R
0
0
29
—
13
—
R
R
0
0
0
Initial
Value
All 0
28
—
12
—
R
R
0
0
27
11
—
—
R
R
0
0
R/W
R
R/W
26
10
—
—
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA Transfer Enable
This bit is used to enable or disable DMA transfer on
the corresponding channel.
Clearing this bit to "0" disables DMA transfer.
Setting this bit to "1" enables DMA transfer. For the
activation of DMA transfer, see section 11.4.3, DMA
Activation.
Even when this bit is clear, the input of a DMA request
to the DMAC can change the value of the DMA
request bit (DREQ).
When the DMA transfer enable clear bit (ECLR) is set
to "1", this bit is automatically cleared to "0" on
detection of the DMA transfer end condition.
Clearing this bit to "0" during DNA transfer can be
used to stop channel operation at the end of the
current single operand transfer. For details, see
section 11.6, Suspending, Restarting, and Stopping of
DMA Transfer.
0: DMA transfer disabled
1: DMA transfer enabled
25
—
—
R
R
0
9
0
ECLR
DEN
R/W
R/W
24
0
8
0
23
—
—
R
R
0
7
0
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
R01UH0026EJ0300 Rev. 3.00
19
—
—
R
R
0
3
0
18
—
—
R
R
0
2
0
SH7201 Group
17
—
—
Sep 24, 2010
R
R
0
1
0
DREQ
DSCLR
R/W
R/W
16
0
0
0