DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 275

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
9.5.2
A description is provided here of the SDRAM controller (SDRAMC) operation enable and
SDRAM bus width settings as well as operations involving SDRAM (read, write, auto-refresh,
self-refresh, initialization sequence, and mode register settings).
(1)
Enabling and disabling SDRAM access is performed by making settings in the individual
SDRAMCm control registers to enable or prohibit SDRAMC operation. SDRAM bus width
settings are also performed by means of the SDRAMCm control registers.
Even if the SDRAMC control register is set to disable SDRAMC operation, refresh operation will
still take place if self-refresh or auto-refresh operation is set as enabled.
(2)
SDRAMC controls the SDRAM by issuing commands each bus cycle. These commands are
defined by combinations of RAS, CAS, WE, CKE, CS, etc.
Table 9.10 lists the commands issued by SDRAMC.
Table 9.10 SDRAMC Commands
[Legend]
H: High level, L: Low level, V: Valid, X: Don't care
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
DSL
ACT
RD
WR
PRA
RFA
MRS
EMRS
RFS
RFX
DPD
DPDX
SDRAM Access Enable/Disable and SDRAM Bus Width Settings
SDRAM Commands
SDRAM Interface
Command
Deselect
Initialize row and bank
Read
Write
Precharge all banks
Auto-refresh
Mode register set
Extended mode
register set
Self-refresh entry
Self-refresh exit
Deep-power-down
Deep-power-down exit
SDCS
H
L
L
L
L
L
L
L
L
H
L
X
SDRAS SDCAS SDWE
L
H
L
X
X
X
H
L
L
L
L
H
X
H
L
L
H
L
L
L
L
X
H
X
X
H
H
L
L
H
L
L
H
X
L
X
Section 9 Bus State Controller (BSC)
SDCKE BA1
X
H
H
H
H
H
H
H
H → L
L → H
L → H
H → L
V
V
X
X
V
X
L
H
X
X
X
X
Page 247 of 1190
BA0
X
V
V
V
X
X
L
L
X
X
X
X