DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1033

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
25.2.9
DSCNT is an 8-bit readable/writable register that selects the clock used to count the oscillation
settling time when the system returns from deep standby mode. DSCNT is initialized to H'00 by a
power-on reset or in deep standby mode but retains its previous value by a manual reset or in
software standby mode. Only byte access is valid.
Since the frequency control register for the CPG (FRQCR) is initialized in deep standby mode, the
frequency of the peripheral clock (Pφ) specified by the CKS[2:0] bits in DSCNT is determined by
the FRQCR's initial value.
Notes: 1. Do not use this setting.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
7 to 3
2 to 0
2. Set the clock so that it is equal to or longer than the oscillation settling time 2 on return
Deep Standby Oscillation Settling Clock Select Register (DSCNT)
Bit Name
⎯
CKS[2:0]
from standby (t
Initial value:
Initial
Value
All 0
000
OSC3
R/W:
Bit:
).
R
0
7
R/W
R
R/W
R
6
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Select
Selects the clock used to count the oscillation settling
time from among eight types clocks derived by
dividing the peripheral clock (Pφ).
The oscillation settling time is calculated as follows:
Oscillation settling time = 1/Pφ × Division ratio
specified by CKS[2:0] × 255 [μs]
The following are the oscillation settling times when
the peripheral clock (Pφ) is running at 5, 10, and 15
MHz.
Setting
value
000:
001:
010:
011:
100:
101:
110:
111:
R
5
0
R
4
0
Clock
select
1 × Pφ*
1/64 × Pφ*
1/128 × Pφ*
1/256 × Pφ*
1/512 × Pφ*
1/1024 × Pφ
1/4096 × Pφ
1/16384 × Pφ
R
0
3
1
1
R/W
1
2
2
0
2
5 MHz
0.05
3.26
6.53
13.06
26.11
52.22
208.90
835.58
CKS[2:0]
R/W
1
0
Oscillation settling time (ms)
R/W
0
0
Section 25 Power-Down Modes
10 MHz
0.03
1.63
3.26
6.53
13.06
26.11
104.45
417.79
Page 1005 of 1190
15 MHz
0.02
1.09
2.18
4.35
8.70
17.41
69.63
278.53