DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1148
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 29 Electrical Characteristics
29.3.2
Table 29.6 Control Signal Timing
Conditions: PV
Notes: 1. The RES, MRES, NMI, IRQ7 to IRQ0 and PINT7 to PINT0 signals are asynchronous
Page 1120 of 1190
Item
RES pulse width
RES setup time*
MRES pulse width
MRES setup time*
NMI pulse width
NMI setup time*
NMI hold time
IRQ7 to IRQ0 pulse width
IRQ7 to IRQ0 setup time*
IRQ7 to IRQ0 hold time
PINT7 to PINT0 setup time*
2. In software standby mode, deep standby mode or when the clock multiplication ratio is
3. In software standby mode or deep standby mode, t
4. In software standby mode or deep standby mode, t
RES
MRES
CKIO
Control Signal Timing
signals. When the setup time is satisfied, change of signal level is detected at the rising
edge of the clock. If not, the detection can be delayed until the rising edge of the next
clock.
changed, t
PV
PV
CC
CC
SS
1
1
= V
= V
− 0.3 V ≤ AV
1
RESW
SS
CC
R = PLLV
R = PLLV
= t
1
1
OSC2
Figure 29.8 Reset Input Timing
(min).
CC
SS
t
CC
≤ PV
RESS
= AV
= 3.0 V to 3.6 V, AV
Symbol
t
t
t
t
t
t
t
t
t
t
t
RESW
RESS
MRESW
MRESS
NMIW
NMIS
NMIH
IRQW
IRQS
IRQH
PINTS
/ t
MRESS
CC
, AV
SS
= 0 V
ref
t
Min.
20*
200
20*
200
20*
150
10
20*
150
10
150
RESW
= 3.0 V to AV
2
3
4
4
/ t
MRESW
Bφ = 60 MHz
CC
Max.
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
= 3.0 V to 3.6 V,
MRESW
NMIW
CC
,
/t
t
RESS
IRQW
= t
/ t
OSC2
MRESS
= t
Unit
t
ns
t
ns
t
ns
ns
t
ns
ns
ns
cyc
cyc
cyc
cyc
OSC3
(min).
R01UH0026EJ0300 Rev. 3.00
(min).
Figure
Figures 29.4, 29.5,
and 29.8
Figures 29.6, 29.9
SH7201 Group
Sep 24, 2010
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