DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 32

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 1 Overview
Page 4 of 1190
Item
Bus state controller
(BSC)
Bus monitor
Features
•
•
•
CSC
⎯ Seven-channel chip select controller (CSC)
⎯ External devices with their bus sizes of 32, 16, or 8 bits can be
⎯ Cycle wait function
⎯ The following features settable for wait controlling
⎯ One-write strobe and byte write strobe modes are available as
⎯ Page read and page write modes are available as page access
SDRAMC
⎯ Two-channel external SDRAM interfaces
⎯ Auto refresh using the internal programmable refresh counter or
⎯ The following features settable
⎯ Random column burst access available (one SDRAM burst length)
⎯ Initialization sequencer issues precharge and auto refresh
Bus monitor function
When an illegal address access or a bus timeout is detected, a bus
error interrupt is generated.
connected
Up to 31 cycles (up to 7 cycles for page access cycle)
Timings of asserting and negating chip select signals
Timings of asserting and negating read/write signals
Timings of starting and stopping data output
write access modes
modes
self refresh mode selectable
Row-column latency, column latency, row-active period, write-
recovery period, row precharge period, auto refresh request
interval, initial precharge cycle count, and initial auto refresh
request interval
commands
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010