DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 184

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 6 Interrupt Controller (INTC)
Figure 6.12 shows the timing for saving to a register bank. Saving to a register bank takes place
between the start of interrupt exception handling and the start of fetching the first instruction in the
exception service routine.
(2)
The RESBANK (restore from register bank) instruction is used to restore data saved in a register
bank. After restoring data from the register banks with the RESBANK instruction at the end of the
interrupt service routine, execute the RTE instruction to return from exception handling.
Page 156 of 1190
IRQ
Instruction (instruction replacing
interrupt exception handling)
Overrun fetch
First instruction in
interrupt service routine
[Legend]
m1:
m2:
m3:
Restoration from Bank
Vector address read
Saving of SR (stack)
Saving of PC (stack)
2 Icyc + 3 Bcyc + 1 Pcyc
Figure 6.12 Bank Save Timing
F
D
F
3 Icyc
3 Icyc + m1 + m2
E
Saved to bank
E
(1) VTO, PR, GBR, MACL
m1
M
(2) R12, R13, R14, MACH
m2
M
(3) R8, R9, R10, R11
m3
M
F
R01UH0026EJ0300 Rev. 3.00
(4) R4, R5, R6, R7
E
D
(5) R0, R1, R2, R3
E
SH7201 Group
Sep 24, 2010