DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 125

IC SH7201 MPU ROMLESS 176LQFP

DS72011RB120FPV

Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet

Specifications of DS72011RB120FPV

Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
SH7201 Group
5.2
5.2.1
Table 5.5 shows the configuration of pins relating to the resets.
Table 5.5
5.2.2
A reset is the highest-priority exception handling source. There are two kinds of resets, power-on
and manual. As shown in table 5.6, the CPU state is initialized by both a power-on reset and a
manual reset. The FPU state is initialized by a power-on reset, but not by a manual reset. On-chip
peripheral module registers except a few registers are initialized by a power-on reset, but not by a
manual reset.
Table 5.6
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Pin Name
Power-on reset
Manual reset
Type
Power-on
reset
Resets
Input/Output Pins
Types of Reset
RES
Low
High
High
Conditions for Transition to Reset State
Pin Configuration
Reset States
H-UDI Command MRES
H-UDI reset assert
command is set
Command other
than H-UDI reset
assert is set
Symbol
RES
MRES
I/O
Input
Input
Function
When this pin is driven low, this LSI shifts to the power-on
reset processing
When this pin is driven low, this LSI shifts to the manual
reset processing.
WDT
Overflow
Power-on
reset
CPU
Initialized Initialized *
Initialized Initialized *
Initialized Initialized *
On-Chip
Peripheral
Modules, I/O Port
Internal States
Section 5 Exception Handling
1
1
1
WRCSR of
WDT, FRQCR
of CPG
Initialized
Initialized
Not initialized
Page 97 of 1190

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