DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 214

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 8 Cache
8.2.2
CCR2 is used to enable or disable the cache locking function for operand cache and is valid in
cache locking mode only. In cache locking mode, the lock enable bit (the LE bit) in CCR2 is set to
1. In non-cache-locking mode, the cache locking function is invalid.
When a cache miss occurs in cache locking mode by executing the prefetch instruction (PREF
@Rn), the line of data pointed to by Rn is loaded into the cache according to bits 9 and 8 (the
W3LOAD and W3LOCK bits) and bits 1 and 0 (the W2LOAD and W2LOCK bits) in CCR2. The
relationship between the setting of each bit and a way, to be replaced when the prefetch instruction
is executed, are listed in table 8.3. On the other hand, when the prefetch instruction is executed
and a cache hit occurs, new data is not fetched and the entry which is already enabled is held. For
example, when the prefetch instruction is executed with W3LOAD = 1 and W3LOCK = 1
specified in cache locking mode while one-line data already exists in way 0 which is specified by
Rn, a cache hit occurs and data is not fetched to way 3.
In the cache access other than the prefetch instruction in cache locking mode, ways to be replaced
by bits W3LOCK and W2LOCK are restricted. The relationship between the setting of each bit in
CCR2 and ways to be replaced are listed in table 8.4.
Programs that change the contents of CCR2 should be placed in an address space that is not
cached, and an address space that is cached should be accessed after reading the contents of
CCR2.
CCR2 is initialized to H'00000000 by a power-on reset and in deep standby but not initialized by a
manual reset or in software standby mode.
Page 186 of 1190
Initial value:
Initial value:
Note:
R/W:
R/W:
*
Bit:
Bit:
The W3LOAD and W2LOAD bits should not be set to 1 at the same time.
Cache Control Register 2 (CCR2)
31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
28
12
R
R
0
0
27
11
R
R
0
0
26
10
R
R
0
0
LOAD*
R/W
W3
25
R
0
9
0
LOCK
R/W
W3
24
R
0
8
0
23
R
R
0
7
0
22
R
R
0
6
0
21
R
R
0
5
0
20
R
R
0
4
0
R01UH0026EJ0300 Rev. 3.00
19
R
R
0
3
0
18
R
R
0
2
0
SH7201 Group
LOAD*
R/W
17
W2
Sep 24, 2010
R
0
1
0
LOCK
R/W
R/W
W2
16
LE
0
0
0