DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 151

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
6.3.4
ICR2 is a 16-bit register that specifies the detection mode for external interrupt input pins PINT7
to PINT0 individually: low level or high level. ICR2 is initialized by a power-on reset or in deep
standby mode.
[Legend]
n = 7 to 0
6.3.5
IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0.
If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after
reading IRQ7F to IRQ0F = 1 cancels the retained interrupts.
IRQRR is initialized by a power-on reset or in deep standby mode.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
15 to 8
7
6
5
4
3
2
1
0
Initial value:
R/W:
Bit:
Interrupt Control Register 2 (ICR2)
IRQ Interrupt Request Register (IRQRR)
Bit Name
⎯
PINT7S
PINT6S
PINT5S
PINT4S
PINT3S
PINT2S
PINT1S
PINT0S
15
—
R
0
14
—
R
0
13
—
R
0
Initial
Value
All 0
0
0
0
0
0
0
0
0
12
—
R
0
11
—
R
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
10
—
R
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
PINT Sense Select
These bits select whether interrupt signals
corresponding to pins PINT7 to PINT0 are detected by
a low level or high level.
0: Interrupt request is detected on low level of PINTn
1: Interrupt request is detected on high level of PINTn
—
R
9
0
input
input
—
R
8
0
PINT
R/W
7S
7
0
PINT
R/W
6S
6
0
PINT
R/W
5S
5
0
Section 6 Interrupt Controller (INTC)
PINT
R/W
4S
4
0
PINT
R/W
3S
3
0
PINT
R/W
2S
2
0
Page 123 of 1190
PINT
R/W
1S
1
0
PINT
R/W
0S
0
0