DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 773

IC SH7201 MPU ROMLESS 176LQFP

DS72011RB120FPV

Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet

Specifications of DS72011RB120FPV

Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
SH7201 Group
17.3.6
SAR is an 8-bit readable/writable register that selects the communications format and sets the
slave address. In slave mode with the I
upper seven bits of the first frame received after a start condition, this module operates as the slave
device.
SAR is initialized to H'00 by a power-on reset or deep standby mode.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
0
Bit
7 to 1
0
Slave Address Register (SAR)
Bit Name
ADZ
Bit Name
SVA[6:0]
FS
Initial value:
Initial
Value
0
Initial
Value
0000000
0
R/W:
Bit:
R/W
7
0
R/W
R/W
R/W
R/W
R/W
2
R/W
C bus format, if the upper seven bits of SAR match the
6
0
Description
General Call Address Recognition Flag
This bit is valid in slave receive mode with the I
format.
[Clearing condition]
[Setting condition]
R/W
5
0
When 0 is written in ADZ after reading ADZ = 1
When the general call address is detected in slave
receive mode
Description
Slave Address
These bits set a unique address in these bits,
differing form the addresses of other slave devices
connected to the I
Format Select
0: I
1: Clocked synchronous serial format is selected
SVA[6:0]
2
R/W
C bus format is selected
4
0
R/W
3
0
R/W
2
0
2
C bus.
R/W
1
0
Section 17 I
R/W
FS
0
0
2
C Bus Interface 3 (IIC3)
Page 745 of 1190
2
C bus

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