DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 776

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 17 I
17.4
The I
mode by setting FS in SAR.
17.4.1
Figure 17.3 shows the I
following a start condition always consists of eight bits.
[Legend]
S:
SLA:
R/W:
A:
DATA: Transfer data
P:
Page 748 of 1190
SDA
SCL
(a) I
(b) I
S
S
1
1
2
2
2
C bus interface 3 can communicate either in I
C bus format (FS = 0)
C bus format (Start condition retransmission, FS = 0)
S
Start condition. The master device drives SDA from high to low while SCL is high.
Slave address
Indicates the direction of data transfer: from the slave device to the master device when
Acknowledge. The receive device drives SDA to low.
Stop condition. The master device drives SDA from low to high while SCL is high.
R/W is 1, or from the master device to the slave device when R/W is 0.
Operation
I
2
SLA
C Bus Interface 3 (IIC3)
SLA
2
C Bus Format
7
7
SLA
1-7
1
1
R/W
R/W
1
1
2
C bus formats. Figure 17.4 shows the I
R/W
8
A
A
1
1
DATA
DATA
A
9
n1
Figure 17.3 I
n
Figure 17.4 I
m1
A
1
A/A
1-7
1
m
DATA
S
1
2
C Bus Formats
2
C Bus Timing
2
C bus mode or clocked synchronous serial
8
SLA
7
A/A
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2
1
9
A
1
2
R/W
P
C bus timing. The first frame
1
1
A
1
1-7
DATA
n: Transfer bit count (n = 1 to 8)
m: Transfer frame count (m
DATA
R01UH0026EJ0300 Rev. 3.00
n2
8
m2
9
A
A/A
SH7201 Group
1
Sep 24, 2010
P
1
P
1)
1)