DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 864

IC SH7201 MPU ROMLESS 176LQFP

DS72011RB120FPV

Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet

Specifications of DS72011RB120FPV

Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 19 Controller Area Network (RCAN-ET)
Bit 0 — Bit Sample Point (BSP = BCR1[0]): Sets the point at which data is sampled. Three-time
sampling is only available when the BRP is programmed to be greater than 4.
• BCR0 (Address = H'006)
Bits 8 to 15 : Reserved. The written value should always be '0' and the returned value is '0'.
Bits 7 to 0—Baud Rate Pre-scale (BRP[7:0] = BCR0 [7:0]): These bits are used to define the
peripheral clock periods contained in a Time Quantum.
Page 836 of 1190
Bit 0: BSP
0
1
Bit 7:
BRP[7]
0
0
0
:
:
1
Initial value:
R/W:
Bit:
Bit 6:
BRP[6]
0
0
0
:
:
1
15
R
0
14
R
0
Bit 5:
BRP[5]
0
0
0
:
:
1
Description
Bit sampling at one point (end of time segment 1) (Initial value)
Bit sampling at three points (rising edge of the last three clock cycles of
PHSEG1)
13
R
0
Bit 4:
BRP[4]
0
0
0
:
:
1
12
R
0
11
R
0
Bit 3:
BRP[3]
0
0
0
:
:
1
10
R
0
Bit 2:
BRP[2]
0
0
0
:
:
1
R
9
0
R
8
0
Bit 1:
BRP[1]
0
0
1
:
:
1
R/W
7
0
R/W
6
0
Bit 0:
BRP[0]
0
1
0
:
:
1
R/W
5
0
R/W
Description
2 × peripheral clock
(Initial value)
4 × peripheral clock
6 × peripheral clock
2 × (register value+1) ×
peripheral clock
512 × peripheral clock
BRP[7:0]
4
0
R01UH0026EJ0300 Rev. 3.00
R/W
3
0
R/W
2
0
SH7201 Group
R/W
Sep 24, 2010
1
0
R/W
0
0

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