DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 355

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
23 to 17 ⎯
16
Bit Name
DREQ
Initial
Value
All 0
0
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA Request
This bit is used to check whether a DMA request is
currently present.
Furthermore, when the software trigger is selected
(DCTG = "000000") by the DMA request source
selection bits (DCTG), DMA requests operate through
this bit.
The value of this bit changes according to the state of
DMA request input to the DMAC regardless of the
settings of the DMAC module activation bit (DMST)
and DMA transfer enable bit (DEN). The conditions for
setting and clearing the bit are determined by the DMA
request source selection bits (DCTG) and input sense
mode selection bits (STRG) as described below.
(a) When software triggering is selected (DCTG =
•
•
"000000") by the DMA request source selection
bits (DCTG).
Condition for setting to "1"
This bit is set to "1" when a "1" is written to it by
software, generating the DMA request.
Condition for clearing to "0"
This bit is cleared to "0" by either of the below
events.
⎯ Software writing a "0" to the bit
⎯ The start of the transfer operation
corresponding to the bit setting
Section 11 Direct Memory Access Controller (DMAC)
Page 327 of 1190