DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 325

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
(3)
For transfers where multiple bus accesses are made (such as burst transfer), the next bus access
might not be terminated when a bus timeout occurs. In this case, a bus timeout may occur
continuously.
Even if a bus timeout occurs continuously, the timeout process of terminating a bus access is
performed in the same way as the first time. However, the status is saved in the bus monitor status
register 1 (SYSCESTS1) or bus monitor status register 2 (SYCBESTS2) only the first time.
10.2.4
The types of detectable bus error depend on the master and access mode.
(1)
Table 10.5 shows the types of bus error that may be generated by accesses from the CPU.
Table 10.5 CPU Access Types and Types of Bus Error Generated
[Legend]
O:
⎯:
Notes: 1. To enable bus error detection, the bus monitor enable register (SYCBEEN) should be
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Access Type
Illegal address access*
Bus timeout*
Bus Timeout Operation in Consecutive Accesses
CPU Transfer Modes and Types of Bus Error Generated
A bus error is generated.
A bus error is not generated.
2. To notify the CPU of a bus error, the 00CPEN bit in the bus error control register
3. The number of bus errors detected is the same as the number of accesses that resulted
Combinations of Masters and Bus Errors
set.
(SYCBESW) should be set to 1.
in an error.
1
1
Normal Access
O*
O*
2
2
Burst Access
O*
O*
2
2
*
*
3
3
Section 10 Bus Monitor
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