DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 627

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
This LSI has an on-chip 2-channel 8-bit timer based on an 8-bit counter. It can be used to count
external events and, using compare-match signals with two registers, as a multifunction timer in a
variety of applications, such as the generation of counter resets, interrupt requests, and pulse
output with a user-defined duty cycle.
Figure 13.1 shows a block diagram of the 8-bit timer.
13.1
• Selection of seven clock sources
• Selection of three ways to clear the counters
• Timer output control by a combination of two compare match signals
• Cascading of two channels (TMR_0 and TMR_1)
• Three interrupt sources
• Generation of trigger to start A/D converter conversion
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
The counters can be driven by one of six internal clock signals (Pφ/8, Pφ/64, Pφ/8192, Pφ/2,
Pφ/32, or Pφ/1024) or an external clock input.
The counters can be cleared on compare match A or B, or by an external reset signal.
The timer output signal in each channel is controlled by a combination of two independent
compare match signals, enabling the timer to output pulses with a desired duty cycle or PWM
output.
Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the
lower 8 bits (16-bit count mode).
TMR_1 can be used to count TMR_0 compare matches (compare match count mode).
Compare match A, compare match B, and overflow interrupts can be requested independently.
Features
Section 13 8-Bit Timers (TMR)
Section 13 8-Bit Timers (TMR)
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