DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 798
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 17 I
17.7
17.7.1
Issue a start (retransmission) or stop condition after the falling edge of the 9th clock has been
recognized. The falling edge of the 9th clock can be recognized by checking the SCLO bit in the
I
certain timing under the following conditions (1 or 2), the start (retransmission) or stop condition
may not be output correctly.
1. SCL takes longer to rise than the period defined in section 17.6, Bit Synchronous Circuit, due
2. The low-level period between the 8th and 9th clock is prolonged by the slave device, which
17.7.2
In multi-master operation, when the transfer rate setting for this module (ICCR1.CKS[3:0]) makes
this LSI slower than the other masters, pulse cycles with an unexpected length will infrequently be
output on SCL.
Be sure to specify a transfer rate that is at least 1/1.8 of the fastest transfer rate among the other
masters.
17.7.3
Reading ICDRR around the falling edge of the 8th clock might fail to fetch the receive data.
In addition, when RCVD is set to 1 around the falling edge of the 8th clock and the receive buffer
full, a stop condition may not be issued.
Use either 1 or 2 below as a measure against the situations above.
1. In master receive mode, read ICDRR before the rising edge of the 8th clock.
2. In master receive mode, set the RCVD bit to 1 so that transfer proceeds in byte units.
17.7.4
In master receive mode operation, set ACKBT before the falling edge of the 8th SCL cycle of the
last data being continuously transferred. Not doing so can lead to an overrun for the slave
transmission device.
Page 770 of 1190
2
C bus control register 2 (ICCR2). When a start (retransmission) or stop condition is issued with a
to the load of the SCL bus (load capacitance or pull-up resistance).
activates the bit synchronous circuit.
Usage Note
Issuance of Stop Condition and Start Condition (Retransmission)
Note on Setting for Multi-Master Operation
Note on Master Receive Mode
Note on Setting ACKBT in Master Receive Mode
2
C Bus Interface 3 (IIC3)
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010
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