DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 464

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Notes: 1. This bit can be set to 1 only once after a power on reset. After 1 is written, 0 cannot be
Table 12.30 Output Level Select Function
Note: The reverse phase waveform initial output value changes to active level after elapse of the
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Bit
3
2
1
0
Bit 1
OLSN
0
1
dead time after count start.
2. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of
3. Clearing the TOCS bit to 0 makes this bit setting valid.
Bit Name
TOCL
TOCS
OLSN
OLSP
Initial Output
High level
Low level
written to the bit.
control.
Initial
Value
0
0
0
0
Active Level
Low level
High level
R/W
R/(W)*
R/W
R/W
R/W
1
Description
TOC Register Write Protection*
This bit selects the enable/disable of write access to the
TOCS, OLSN, and OLSP bits in TOCR1.
0: Write access to the TOCS, OLSN, and OLSP bits is
1: Write access to the TOCS, OLSN, and OLSP bits is
TOC Select
This bit selects either the TOCR1 or TOCR2 setting to
be used for the output level in complementary PWM
mode and reset-synchronized PWM mode.
0: TOCR1 setting is selected
1: TOCR2 setting is selected
This bit selects the reverse phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 12.30.
This bit selects the positive phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 12.31.
Output Level Select N*
Output Level Select P*
Up Count
High level
Low level
enabled
disabled
Function
Compare Match Output
3
3
Down Count
Low level
High level
2
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010