DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 848
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 19 Controller Area Network (RCAN-ET)
• Mailbox-0
Note: MBC[1] of MB0 is always "1".
• Mailbox-15 to 1
NMC (New Message Control): When this bit is set to '0', the Mailbox of which the RXPR or
RFPR bit is already set does not store the new message but maintains the old one and sets the
UMSR correspondent bit. When this bit is set to '1', the Mailbox of which the RXPR or RFPR bit
is already set overwrites with the new message and sets the UMSR correspondent bit.
Important: Please note that if a remote frame is overwritten with a data frame or vice versa could
be that both RXPR and RFPR flags (together with UMSR) are set for the same Mailbox. In this
case the RTR bit within the Mailbox Control Field should be relied upon.
ATX (Automatic Transmission of Data Frame): When this bit is set to '1' and a Remote Frame
is received into the Mailbox DLC is stored. Then, a Data Frame is transmitted from the same
Mailbox using the current contents of the message data and updated DLC by setting the
corresponding TXPR automatically. The scheduling of transmission is still governed by ID
priority or Mailbox priority as configured with the Message Transmission Priority control bit
(MCR.2). In order to use this function, MBC[2:0] needs to be programmed to be B'001. When a
transmission is performed by this function, the DLC (Data Length Code) to be used is the one that
has been received. Application needs to guarantee that the DLC of the remote frame correspond to
the DLC of the data frame requested.
Important: When ATX is used and MBC = B'001 the filter for the IDE bit cannot be used since
ID of remote frame has to be exactly the same as that of data frame as the reply message.
Page 820 of 1190
NMC
0
1
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
15
15
R
R
0
0
0
0
Description
Overrun mode (Initial value)
Overwrite mode
14
14
R
R
0
0
0
0
NMC
NMC
R/W
R/W
13
13
0
0
R/W
ATX DART
12
12
R
0
0
0
R/W
11
11
R
0
0
0
R/W
R/W
10
10
1
1
MBC[2:0]
MBC[2:0]
R/W
R/W
9
1
9
1
R/W
R/W
8
1
8
1
R
R
7
0
0
7
0
0
R
R
6
0
0
6
0
0
R
R
5
0
5
0
0
0
R
R
4
0
4
0
0
0
R01UH0026EJ0300 Rev. 3.00
R/W
R/W
3
0
3
0
R/W
R/W
DLC[3:0]
DLC[3:0]
2
0
2
0
SH7201 Group
R/W
R/W
Sep 24, 2010
1
0
1
0
R/W
R/W
0
0
0
0
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