DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 87

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
2.4.10
Table 2.19 Bit Manipulation Instructions
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Instruction
BAND.B
BANDNOT.B #imm3,@(disp12,Rn)
BCLR.B
BCLR
BLD.B
BLD
BLDNOT.B
BOR.B
BORNOT.B
BSET.B
BSET
BST.B
BST
BXOR.B
Bit Manipulation Instructions
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,Rn
#imm3,@(disp12,Rn)
#imm3,Rn
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,Rn
#imm3,@(disp12,Rn)
#imm3,Rn
#imm3,@(disp12,Rn)
Instruction Code
0011nnnn0iii1001
0100dddddddddddd
0011nnnn0iii1001
1100dddddddddddd
0011nnnn0iii1001
0000dddddddddddd
10000110nnnn0iii
0011nnnn0iii1001
0011dddddddddddd
10000111nnnn1iii
0011nnnn0iii1001
1011dddddddddddd
0011nnnn0iii1001
0101dddddddddddd
0011nnnn0iii1001
1101dddddddddddd
0011nnnn0iii1001
0001dddddddddddd
10000110nnnn1iii
0011nnnn0iii1001
0010dddddddddddd
10000111nnnn0iii
0011nnnn0iii1001
0110dddddddddddd
Operation
(imm of (disp + Rn)) & T → T
~(imm of (disp + Rn)) & T → T
0 → (imm of (disp + Rn))
0 → imm of Rn
(imm of (disp + Rn)) → T
imm of Rn → T
~(imm of (disp + Rn))
( imm of (disp + Rn)) | T → T
~( imm of (disp + Rn)) | T → T
1 → ( imm of (disp + Rn))
1 → imm of Rn
T → (imm of (disp + Rn))
T → imm of Rn
(imm of (disp + Rn)) ^ T → T
→ T
Execu-
tion
Cycles
3
3
3
1
3
1
3
3
3
3
1
3
1
3
Operation
result
Ope-ration
result
⎯
⎯
Operation
result
Operation
result
Operation
result
Operation
result
Operation
result
⎯
⎯
⎯
⎯
Operation
result
T Bit
SH2,
SH2E
Page 59 of 1190
Section 2 CPU
Compatibility
SH4
SH-2A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes