DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1020

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 25 Power-Down Modes
Table 25.1 States of Power-Down Modes
Notes: 1. The pin state is retained or set to high impedance. For details, see appendix A, Pin
Page 992 of 1190
Power-
Down
Mode
Sleep
mode
Software
standby
mode
Deep
standby
mode
Module
standby
function
Transition
Conditions
Execute SLEEP
instruction with
STBY bit in STBCR
cleared to 0
Execute SLEEP
instruction with
STBY bit in STBCR
set to 1 and DEEP
bit to 0
Execute SLEEP
instruction with
STBY and DEEP bits
in STBCR set to 1
Set the MSTP bits in
STBCR2 to STBCR5
to 1
2.
3. Setting bits RAMKP3 to RAMKP0 in the RAMKP register to 1 enables the retention of
4. Deep standby mode can be canceled by an interrupt (NMI or IRQ) or a reset (manual
States.
data in the corresponding area in the on-chip RAM during the transition to deep standby
mode. However, when deep standby mode is canceled by a power-on reset, the
contents in the corresponding on-chip RAM area are not retained.
reset or power-on reset). However, IRQ is reset only by PE7 to PE0 and PC25 to PC22.
When deep standby mode is canceled by NMI interrupt or IRQ interrupt, reset exception
handling is executed instead of interrupt exception handling. These are power-on reset
exception handlings including a manual reset.
RTC operates when the START bit in the RCR2 register is set to 1. For details, see
section 15, Realtime Clock (RTC).
CPG CPU
Runs Halts Held
Halts Halts Held
Halts Halts Halts
Runs Runs Held
CPU
Register
On-Chip
RAM
Runs
Halts
(contents
are held)
Halts
(contents
are
held*
Runs
3
)
State*
On-Chip
Peripheral
Modules
Runs
Halts
Halts
Specified
module
halts
1
RTC
Runs*
Runs*
Runs*
Halts
2
2
2
Power
supply
Runs
Runs
Halts
Runs
External
Memory
Auto-
refreshing
Self-
refreshing
Self-
refreshing
Auto-
refreshing
R01UH0026EJ0300 Rev. 3.00
Canceling
Procedure
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Interrupt
Manual reset
Power-on reset
Bus error
NMI interrupt
IRQ interrupt
Manual reset
Power-on reset
NMI interrupt*
IRQ interrupt*
for PE7 to PE4 and
PC25 to PC22)
Manual reset*
Power-on reset*
Clear MSTP bit to 0
Power-on reset (only
for RTC, H-UDI, UBC,
DMAC, and AUD-II)
SH7201 Group
Sep 24, 2010
4
4
4
(only
4