DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 733
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 733 of 1222
- Download datasheet (8Mb)
SH7201 Group
16.3.12 Line Status Register (SCLSR)
The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can
be cleared to 0 only if it has first been read (after being set to 1).
SCLSR is initialized to H'0000 by a power-on reset or in deep standby mode.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
15 to 1
0
Initial value:
Note: *
R/W:
Bit:
Only 0 can be written to clear the flag after 1 is read.
Bit Name
—
ORER
15
—
R
0
14
—
R
0
13
—
R
0
Initial
Value
All 0
0
12
—
R
0
11
—
R
0
R/W
R
R/(W)* Overrun Error
10
—
R
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Indicates the occurrence of an overrun error.
0: Receiving is in progress or has ended normally*
[Clearing conditions]
•
•
1: An overrun error has occurred*
[Setting condition]
•
Notes: 1. Clearing the RE bit to 0 in SCSCR does
—
R
9
0
ORER is cleared to 0 when the chip is a power-on
reset
ORER is cleared to 0 when 0 is written after 1 is
read from ORER.
ORER is set to 1 when the next serial receiving is
finished while the receive FIFO is full of 16-byte
receive data.
—
R
8
0
Section 16 Serial Communication Interface with FIFO (SCIF)
2. The receive FIFO data register (SCFRDR)
—
R
7
0
not affect the ORER bit, which retains its
previous value.
retains the data before an overrun error
has occurred, and the next received data
is discarded. When the ORER bit is set to
1, the SCIF cannot continue the next
serial reception.
—
R
6
0
—
R
5
0
—
R
4
0
—
R
3
0
2
R
2
—
0
Page 705 of 1190
R
1
—
0
R/(W)*
ORER
0
0
1
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