DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 775
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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SH7201 Group
17.3.10 NF2CYC Register (NF2CYC)
NF2CYC is an 8-bit readable/writable register that selects the range of the noise filtering for the
SCL and SDA pins. For details of the noise filter, see section 17.4.7, Noise Filter.
NF2CYC is initialized to H'02 by a power-on reset or in deep standby mode.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
7 to 2
1
0
Bit Name
⎯
⎯
NF2CYC
Initial value:
Initial
Value
All 0
1
0
R/W:
Bit:
—
R
7
0
R/W
R
R
R/W
—
R
6
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Reserved
This bit is always read as 0. The write value should
always be 1.
Noise Filtering Range Select
0: The noise less than one cycle of the peripheral clock
1: The noise less than two cycles of the peripheral clock
—
R
can be filtered out
can be filtered out
5
0
—
R
0
4
—
R
3
0
—
R
2
0
—
R
1
1
Section 17 I
R/W
CYC
NF2
0
0
2
C Bus Interface 3 (IIC3)
Page 747 of 1190
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