DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 163

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
6.4.5
PINT interrupts are input from pins PINT7 to PINT0. As regard to the setting method of pins
PINT7 to PINT0, see section 23, Pin Function Controller (PFC). Input of the interrupt requests is
enabled by the PINT enable bits (PINT7E to PINT0E) in the PINT interrupt enable register
(PINTER). For the PINT7 to PINT0 interrupts, low-level or high-level detection can be selected
individually for each pin by the PINT sense select bits (PINT7S to PINT0S) in interrupt control
register 2 (ICR2). A single priority level in a range from 0 to 15 can be set for all PINT7 to PINT0
interrupts by bits 15 to 12 in interrupt priority register 05 (IPR05).
When using low-level sensing for the PINT7 to PINT0 interrupts, an interrupt request signal is
sent to the INTC while the PINT7 to PINT0 pins are low. An interrupt request signal is stopped
being sent to the INTC when the PINT7 to PINT0 pins are driven high. The status of the interrupt
requests can be checked by reading the PINT interrupt request bits (PINT7R to PINT0R) in the
PINT interrupt request register (PIRR). The above description also applies to when using high-
level sensing, except for the polarity being reversed. The PINT interrupt exception handling sets
the I3 to I0 bits in SR to the priority level of the PINT interrupt.
When restoring from the service routine of PINT interrupt exception handling, execute the RTE
instruction after an interrupt request has been cleared in the PINT interrupt request register
(PIRR).
6.4.6
On-chip peripheral module interrupts are generated by the following on-chip peripheral modules:
• A/D converter (ADC)
• Multi-function timer pulse unit 2 (MTU2)
• Realtime clock (RTC)
• Watchdog timer (WDT)
• I
• Direct memory access controller (DMAC)
• Serial communication interface with FIFO (SCIF)
• Controller area network (RCAN-ET)
• Serial sound interface (SSI)
• 8-bit timer (TMR)
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
2
C bus interface 3 (IIC3)
PINT Interrupts
On-Chip Peripheral Module Interrupts
Section 6 Interrupt Controller (INTC)
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