DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 359

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
Note: When the software trigger is selected as the DMA request source, the DMA request bit
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
0
(DREQ) can be set to "1" regardless of the settings of the DMA transfer enable bit (DEN)
and DMAC module activation bit (DMST) and whether or not a transfer operation is
currently in progress. However, even if the software trigger is selected as the DMA request
source, only clear the DMA request bit (DREQ) to "0" or write to the DMAC internal state
clearing bit (DSCLR) when a transfer operation is not in process on the corresponding
channel (the corresponding DASTS bit in the DMA arbitration status register (DMASTS) is
"0") and DMA transfer has been disabled (DMST in the DMA activation control register
(DMSCNT) or DEN in the DMA control register B (DMCNTBn) is set to "0"). Operation is not
guaranteed if this register is written to when these conditions are not satisfied.
Bit Name
DSCLR
Initial
Value
0
R/W
R/W
Description
DMA Internal State Clear
Writing a "1" to this bit stops DMA transfer in the
middle of a sequence of DMA transfer, suspending the
remainder of the transfer and initializing the internal
state of the DMAC. Writing a "1" to this bit only clears
the transfer state of the DMAC internal circuit. The
other registers are not initialized. Writing "0" is invalid
and a "1" written to this bit is not retained. This bit is
always read as "0".
Note: This bit must only be written to when the
When reading:
Always read as "0"
When writing:
0: Invalid
1: Initializes the DMAC's internal state
corresponding channel is not in the midst of
single operand transfer (DASTS in the channel
corresponding to the DMA arbitration status
register (DMASTS) is "0") and DMA transfer has
been disabled (DMST in the DMA activation
control register (DMSCNT) or DEN in DMA
control register B (DMCNTBn) is set to "0").
Operation is not guaranteed when this bit is
written to while these conditions do not apply.
Section 11 Direct Memory Access Controller (DMAC)
Page 331 of 1190