DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1189

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
All
2.1.3 System Registers
(3) Program Counter (PC)
2.4.2 Data Transfer Instructions
Table 2.11 Data Transfer
Instructions
3.1 Features
3.2.2 Non-Numbers (NaN)
Item
Main Revisions for This Edition
Page
—
22
23
46
63
66
Revision (See Manual for Details)
Company name and brand names amended
(Before) Renesas Technology Corp. →
(After) Renesas Electronics Corporation
Description amended
... return address from a subroutine procedure. PC
points four bytes ahead of the current instruction and
controls the flow of the processing.
Description amended
PC points four bytes ahead of the instruction being
executed.
Table amended
Description deleted
•
Description amended
•
Instruction
MOVML.L @R15+,Rn
MOVMU.L @R15+,Rn
Comprehensive instructions: Single-precision,
double-precision, and system control
When the EN.V bit in FPSCR is 1, an invalid
operation exception will generate FPU exception
processing. In this case, the contents of the
operation destination register are unchanged.
Instruction Code
0100nnnn11110101 (R15)
0100nnnn11110100 (R15)
Operation
(R15)
(R15)
Note: When Rn = R15, read
(R15)
R15
(R15)
(R15)
Note: When Rn = R15, read
Rn as PR
Rn as PR
:
:
R0, R15 + 4
R1, R15 + 4
Rn
Rn, R15 + 4
Rn + 1, R15 + 4
R14, R15 + 4
PR
Main Revisions for This Edition
R15
R15
R15
R15
Execu-
tion
Cycles
1 to 16
1 to 16
Page 1161 of 1190
T Bit
SH2,
SH2E SH4
Compatibility
SH-2A
Yes
Yes