DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 130

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 5 Exception Handling
5.3.2
When an address error occurs, address error exception handling starts after the bus cycle in which
the address error occurred ends* and execution of the instruction being executed completes. The
CPU operates as follows.
1. The exception service routine start address which corresponds to the address error that
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
4. After jumping to the address fetched from the exception handling vector table, program
Note: * In the case of address error related to data read/write. In the case of address error
Page 102 of 1190
occurred is fetched from the exception handling vector table.
instruction to be executed after the last executed instruction.
execution starts. The jump that occurs is not a delayed branch.
Address Error Exception Handling
related to instruction fetch, if the bus cycle in which the address error occurred doesn't
end until the entire three above-mentioned operations end, the CPU will start address
error exception handling again until the bus cycle in which the address error occurred
ends.
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010