DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 266

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
1. Ts (Internal Bus Access Start)
2. Tw1 to Twn (Read Cycle Wait, Write Cycle Wait)
3. Tend (Wait End Cycle)
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This is a bus access request cycle initiated by the internal bus master and with the external bus
as the target. CSn is always high during this cycle. In the next cycle A27 to A0 and the write
data change.
These are the cycles between internal bus access start and the wait end cycle. A duration of
from 0 to 31 clocks may be selected. During this interval the CSn, RD, and WR control signals
are asserted (low level) in accordance with the wait settings. The assert timing can be
controlled using the CS assert wait, RD assert wait, WR assert wait, and write data output wait
bits in CSn control registers 1 and 2. The number of wait cycles can be set to from 0 to 7
clocks, with the count starting from the cycle following internal bus access start (Ts). The
number of clocks selected must be no greater than the number of read/write cycle wait cycles.
This is the final cycle in a series of read cycle wait or write cycle wait cycles. The RD or WR
signal is negated (high level) in the next cycle.
CKIO
A27 to A0
CSn
RD
WR
D31 to D0
Ts
Figure 9.3 Basic Bus Timing (Write Operation)
Tw1 Tw2
CS assert wait
WR assert wait
Write data output wait
Write cycle wait
Twn
Tend
Tn1
Write data output delay cycle
cycle during write
CS delay
Tnm
R01UH0026EJ0300 Rev. 3.00
Start enable point
of next bus access
SH7201 Group
Sep 24, 2010