DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 160

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 6 Interrupt Controller (INTC)
6.3.13
DMA transfer request enable register 3 (DREQER3) is an 8-bit readable/writable register that
enables/disables the ADC, MTU2 (channels 0 to 4), and RCAN-ET (channels 0 and 1) DMA
transfer requests, and enables/disables CPU interrupt requests.
DMA transfer request enable register 3 is initialized by a power-on reset or in deep standby mode.
Page 132 of 1190
Bit
7
6
5
4
3
2
1
0
Bit Name
ADC
MTU2 4ch
MTU2 3ch
MTU2 2ch
MTU2 1ch
MTU2 0ch
RCAN-ET 1ch 0
RCAN-ET 0ch 0
DMA Transfer Request Enable Register 3 (DREQER3)
Initial value:
Initial
Value
0
0
0
0
0
0
R/W:
Bit:
ADC
R/W
0
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MTU2
R/W
4ch
0
6
Description
DMA Transfer Request Enable Bits
These bits enable/disable DMA transfer requests, and
enable/disable CPU interrupt requests.
0: DMA transfer request disabled, CPU interrupt
1: DMA transfer request enabled, CPU interrupt request
MTU2
R/W
3ch
0
5
request enabled
disabled
MTU2
R/W
2ch
0
4
MTU2
R/W
1ch
0
3
MTU2
R/W
0ch
0
2
RCAN-ET
R/W
1ch
1
0
RCAN-ET
R/W
0ch
0
0
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010