DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 290

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
Page 262 of 1190
Note : * Driving the DQM pin high before the initialization sequence is recommended
Reset
Specify all SDRAM control pins as port outputs with the PFC
setting of PORTC to output high level
Channel m settings
(1) Confirm that all status bits in SDSTR have been cleared to 0
(2) Make settings to SDmMOD mode register
(3) Set DRAS, DRCD, DPCG, DCL, and DWR bits in SDmTR
(4) Set DSZ bits in SDmADR
Enable access
SDRAMCm control register operation enable setting
Dummy-read SDRAM area of all channels to be used
Disable access
SDRAMCm control register operation disable setting
Specify SDRAM control pins (except DQM pin*) as SDRAM
with the PFC setting of PORTC
Initialization sequence
(1) Set DPC, DARFC, and DARFI bits in SDIR0
(2) Set DINIRQ bit in SDIR1 to 1
(3) Wait for DINIST bit in SDIR1 to be cleared to 0
Channel m settings
(1) Confirm that all status bits in SDSTR have been cleared to 0
(2) Make settings to SDmMOD mode register
(3) Set DRAS, DRCD, DPCG, DCL, and DWR bits in SDmTR
(4) Set DSZ bits in SDmADR
Start auto-refresh
Set DRFEN bit in SDRFCNT1 to 1
Specify DQM pin as DQM* with the PFC setting of PORTC
Enable access
SDRAMCm control register operation enable setting
SDRAM access enabled
for some SDRAM modules. In this case, the setting may be necessary.
Figure 9.26 SDRAMC Setting Procedure
Perform settings
for all channels
to be used
Perform settings
for all channels
to be used
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010