DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 139

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
4. After jumping to the address fetched from the exception handling vector table, program
The FPU exception flag field (Flag) of FPSCR is always updated regardless of whether or not an
FPU exception handling has been accepted, and remains set until explicitly cleared by the user
through an instruction. The FPU exception source field (Cause) of FPSCR changes each time a
floating point operation instruction is executed.
When the V bit in the FPU exception enable field (Enable) of FPSCR is set and the QIS bit in
FPSCR is also set, FPU exception handling is generated when qNAN or ±∞ is input to a floating
point operation instruction source.
5.8
When an address error, bus error, FPU exception, register bank error (overflow), or interrupt is
generated immediately after a delayed branch instruction, it is sometimes not accepted
immediately but stored instead, as shown in table 5.11. When this happens, it will be accepted
when an instruction that can accept the exception is decoded.
Table 5.11 Exception Source Generation Immediately after Delayed Branch Instruction
Note:
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Point of Occurrence
Immediately after a
delayed branch
instruction *
execution starts. The jump that occurs is not a delayed branch.
* Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
When Exception Sources Are Not Accepted
BRAF.
Address
Error
Not accepted
Bus Error
Not accepted Not accepted Not accepted Not accepted
Exception Source
FPU
Exception
Register
Bank Error
(Overflow)
Section 5 Exception Handling
Interrupt
Page 111 of 1190