DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 496

IC SH7201 MPU ROMLESS 176LQFP

DS72011RB120FPV

Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet

Specifications of DS72011RB120FPV

Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(1)
Figure 12.20 shows an example of the setting procedure for cascaded operation.
(2)
Figure 12.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for
TCNT_1 and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
Page 468 of 1190
Example of Cascaded Operation Setting Procedure
Cascaded Operation Example (a)
TCLKC
TCLKD
TCNT_2
TCNT_1
<Cascaded operation>
Cascaded operation
Set cascading
Figure 12.20 Cascaded Operation Setting Procedure
Start count
FFFD
Figure 12.21 Cascaded Operation Example (a)
0000
FFFE
FFFF
[1]
[2]
0000
[1] Set bits TPSC2 to TPSC0 in the channel 1
[2] Set the CST bit in TSTR for the upper and
0001
TCR to B'1111 to select TCNT_2 overflow/
underflow counting.
lower channel to 1 to start the count
operation.
0001
0002
0001
0000
R01UH0026EJ0300 Rev. 3.00
FFFF
0000
SH7201 Group
Sep 24, 2010

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